In computing, interleaved memory is a design which compensates for the relatively gradual velocity of dynamic random-access memory (DRAM) or core memory, by spreading memory addresses evenly throughout memory banks. That manner, contiguous memory reads and writes use each memory financial institution in turn, resulting in larger memory throughput as a result of decreased ready for memory banks to turn into prepared for the operations. It's completely different from multi-channel memory architectures, primarily as interleaved memory doesn't add extra channels between the primary memory and the memory controller. However, channel interleaving can also be doable, Memory Wave Program for instance in freescale i.MX6 processors, which allow interleaving to be accomplished between two channels. With interleaved memory, memory addresses are allocated to each Memory Wave financial institution in turn. For instance, in an interleaved system with two memory banks (assuming phrase-addressable memory), if logical address 32 belongs to financial institution 0, then logical address 33 would belong to financial institution 1, logical handle 34 would belong to bank 0, and so on. An interleaved memory is alleged to be n-manner interleaved when there are n banks and memory location i resides in bank i mod n.
Interleaved memory results in contiguous reads (that are common both in multimedia and execution of programs) and contiguous writes (that are used frequently when filling storage or communication buffers) actually utilizing each memory financial institution in turn, as an alternative of using the same one repeatedly. This ends in significantly increased Memory Wave Program throughput as each bank has a minimal ready time between reads and writes. Major memory (random-entry memory, RAM) is usually composed of a set of DRAM memory chips, where plenty of chips might be grouped collectively to form a memory bank. It's then doable, with a memory controller that helps interleaving, to lay out these memory banks in order that the memory banks will be interleaved. Information in DRAM is stored in models of pages. Every DRAM bank has a row buffer that serves as a cache for accessing any page within the financial institution. Earlier than a web page in the DRAM bank is read, it is first loaded into the row-buffer.
If the web page is immediately learn from the row-buffer (or a row-buffer hit), it has the shortest memory entry latency in one memory cycle. If it's a row buffer miss, which can be called a row-buffer battle, it is slower because the brand new web page needs to be loaded into the row-buffer before it is learn. Row-buffer misses happen as access requests on totally different memory pages in the same financial institution are serviced. A row-buffer conflict incurs a substantial delay for a memory entry. In distinction, memory accesses to completely different banks can proceed in parallel with a excessive throughput. The issue of row-buffer conflicts has been nicely studied with an efficient answer. The scale of a row-buffer is generally the scale of a memory web page managed by the working system. Row-buffer conflicts or misses come from a sequence of accesses to distinction pages in the identical memory financial institution. The permutation-based interleaved memory methodology solved the issue with a trivial microarchitecture value.
Sun Microsystems adopted this the permutation interleaving methodology shortly of their merchandise. This patent-free method might be discovered in many industrial microprocessors, such as AMD, Intel and NVIDIA, for embedded techniques, laptops, desktops, and enterprise servers. In traditional (flat) layouts, memory banks could be allocated a contiguous block of memory addresses, which is very simple for the memory controller and provides equal performance in fully random entry situations, when in comparison with efficiency levels achieved via interleaving. Nevertheless, in reality memory reads are hardly ever random because of locality of reference, and optimizing for close collectively access gives much better efficiency in interleaved layouts. The best way memory is addressed has no effect on the access time for memory locations that are already cached, having an impression only on memory areas which need to be retrieved from DRAM. Zhao Zhang, Zhichun Zhu, and Xiaodong Zhang (2000). A Permutation-primarily based Web page Interleaving Scheme to cut back Row-buffer Conflicts and Exploit Data Locality. Department of Laptop Science and Engineering, Faculty of Engineering, Ohio State University. Mark Smotherman (July 2010). "IBM Stretch (7030) - Aggressive Uniprocessor Parallelism".