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<br>AUSTIN, Texas, Might 2, 2018 - The DDR PHY Interface (DFI) Group at this time launched version 5.Zero of the specification for interfaces between high-pace memory controllers and physical (PHY) interfaces to help the necessities of future cell and server [Memory Wave](http://kumkangenc.com/bbs/board.php?bo_table=inquiry&wr_id=624108) requirements. The DFI specifications, extensively adopted throughout the memory industry, allow higher interoperability. The DFI Group included several interface improvements in this latest specification. The brand new version of the specification provides protocol help for the most recent DDR and low-power memory applied sciences. Earlier variations of the specification outlined memory coaching across the interface between the memory controller and the PHY. The new specification fully transitions to PHY-independent training mode the place the PHY trains the memory interface without involving the controller. Different interface improvements include lower energy enhancements, offering a PHY-unbiased boot sequence, increasing frequency change support, and defining new controller-to-PHY interface interactions. "The industry is beginning to embrace new low-energy and DDR memory technologies, including excessive-efficiency devices such as servers, storage, and networking |
